1. Technical Field
The present invention relates to a method of fabricating a semiconductor device, adopted to a process of forming by plating an electro-conductive film on an insulating film having a plurality of recesses formed therein, and a plating apparatus.
2. Related Art
In semiconductor devices using copper interconnect, there is an increasing demand on improved performance in filling of holes and trenches by copper plating, with progress of scaling of interconnect patterns as a result of shrinkage of design rule.
U.S. Pat. No. 6,319,831 and U.S. Pat. No. 6,140,241 describe procedures in which a first plating is carried out at a lower current density, and a second plating is then carried out at a higher current density.
Japanese Laid-Open Patent Publication No. 2001-123298 describes a technique of electrolytic plating. In this document, a mathematical relationship between current density and potential of electrode is determined by using an electrode composed of the same material with an object to be plated, and then the object to be plated is polarized in a plating bath at an arbitrary potential or current. A current value and potential value of the polarized object are measured, then an area of the object to be plated is calculated based on the mathematical relationship, the current value and potential value. Thus the calculated area of the object to be plated is used for electrolytic plating. More specifically, an interconnect pattern is formed on a substrate by a photolithographic technique using a photosensitive resist for plating, and the current value is then measured by allowing the substrate to polarize, in order to determine the exposed area of the electrode not covered by the photosensitive resist, that is, the area to be plated. The area of the substrate to be plated is then calculated based on the current value. Current value for the plating is then determined based on the calculated area.
Japanese Laid-Open Patent Publication No. 2005-264271 describes a method of fabricating a semiconductor device which includes a step of acquiring a ratio of fine recesses having width not larger than a first reference width in a layer having a plurality of recesses formed therein, a step of determining integrated current value necessary for filling up the recesses with an electro-conductive material based on the ratio, and a step of forming an electro-conductive layer by the electroplating process, based on thus-determined integrated current value. It is described that the method can successfully form an electroplated film with an appropriate thickness.
Japanese Laid-Open Patent Publication No. 2006-60011 describes a method of fabricating a semiconductor device which includes a first plating process allowing current having a first current density to flow using as an electrode a seed film formed on the surface of an insulating film and in openings, so as to deposit an electro-conductive material in the openings by the plating process, a second plating process following the first plating process, allowing current having a current density smaller than the first current density to flow so as to deposit the electro-conductive material on the surface of the insulating film by the plating process, and an annealing process following the second plating process, annealing the product.
Japanese Laid-Open Patent Publication No. 2005-39142 describes a method of fabricating a semiconductor device which includes a first step allowing electrolytic plating to proceed so as to fill at least either one of interconnect trenches and holes formed in an insulating film on a semiconductor substrate with an electro-conductive layer, under a condition such that an integrated current density, which is a product of current density (a current value per unit area of a cathode electrode, that is a wafer to be plated) and plating time, is kept at a predetermined value, and a second step allowing plating to proceed under a condition such that the current density is kept smaller than that in the first step. It is described that adoption of the electrolytic plating method in this patent publication can successfully improve filling performance of the electro-conductive layer formed in the interconnect trenches and holes, and can improve uniformity of bottom-up performance over the entire surface of wafer.
Japanese Laid-Open Patent Publication No. 2004-270028 describes a method of damascene copper plating, including a step of allowing current to flow, only in the direction opposite to the current direction corresponding to the growth of the plated film during plating. The method can prevent the plated film from piling up in the area where the interconnect is densely distributed, and can consequently avoid increase in the cost due to increase in the process time of CMP.
A plating apparatus generally has a preset recipe describing predetermined reference current density applied to the works to be plated and plating time. On the other hand, a substrate of a semiconductor device may have various interconnect patterns depending on design. A substrate having a lot of fine patterns need longer time for the plating, as compared with a substrate having only a less amount of fine patterns. For this reason, plating various substrates of semiconductor devices having different designs under the same current density and the same duration of time has a problem in that the semiconductor devices having a less amount of fine patterns causes excessive growth of the plated film, if the plating is allowed to proceed on the basis of the semiconductor devices having a lot of fine patterns. The excessive growth of the plated film is causative of unnecessary costs due to unnecessarily large consumption of plating material, takes a longer time for the succeeding CMP or other processing, and results in lowering in throughput. On the contrary, plating on the basis of the semiconductor devices having only a less amount of fine patterns raises a problem in that the semiconductor devices having a lot of fine patterns suffers from insufficient formation of the plated film. In particular, the fine recesses cannot thoroughly be plated, leaving voids or the like formed in the recesses. These problems have been remained unsolved.
After extensive investigations into the above-described phenomena, the present inventors found out that, when the recesses of the semiconductor devices are filled with an electro-conductive material by plating, the above-described problems are ascribable to large difference in effective surface area for the plating, as a result of large difference in the area of the side walls of the recesses depending on the density of interconnect pattern.
However, these problems have been left unsolved. For example, Japanese Laid-Open Patent Publication No. 2001-123298 determines a current value for plating based on the area of the electrode to be plated, but makes no consideration on characteristics of filling of the recesses with the electro-conductive material by plating. In other words, accurate correction cannot be given, because there is no consideration on the area of side walls of the recesses. Japanese Laid-Open Patent Publication No. 2005-264271 determines the integrated current value depending on ratio of the fine recesses to the layer, but makes no consideration on the effective surface area for plating, and therefore gives no accurate correction.